AI PCB design rule checks: what AI adds, and what it cannot replace

KiCad's manual describes its DRC as checking for incorrect and missing connections, copper clearance and minimum width violations, and it supports custom rules for anything the basic constraints do not cover. Every serious ECAD has a check like it. The rules come from your manufacturer's capabilities and your own electrical constraints, and the check either passes or lists violations.

That is not a job for a language model. A model might miss a 0.1 mm clearance violation that a geometry check would always catch. AI helps with the layer above: is the regulator's input capacitor the value the datasheet asks for, is every I2C line pulled up, is that MOSFET's gate driven hard enough. Those are review questions, the kind a senior engineer usually answers.

Because a problem caught at the edit that caused it is cheaper than one found in a report afterwards. Cherry Blossom generates the board from a plain-English description, and each AI edit goes through a verification gate against manufacturing rules before it lands. Footprints come from real part data rather than a model's guess, and a DRC runs before the board can be ordered through the PCBWay hand-off. The design check page covers what it looks at.

You can still export Gerbers and run them through JLCDFM or any other checker, and you can export an editable KiCad project to run KiCad's DRC with your own rules.

Flux says its Copilot checks each IC pin for a decoupling capacitor where one is needed, checks the capacitor's voltage and capacitance, confirms pull-up and pull-down resistors are present and correctly valued, and reads datasheets to verify component ratings. It works inside Flux on Flux projects. Its own docs add that it primarily works with schematics and has limited understanding of PCB layout and trace positioning.

Traceformer takes a KiCad project (through a plugin) or an Altium export, fetches the datasheets, and returns findings that cite datasheet pages. Its site is explicit that it focuses on datasheet and application-level issues, not electrical rule checking or simulation. We think that is the right split.

KiCad MCP servers let a general assistant like Claude run ERC and DRC and read the result. kicad-mcp-pro ships read-only review tools by default and describes its signal-integrity, power-integrity, EMC and thermal tools as first-order estimates of roughly 5 to 10% accuracy, not a substitute for a field solver. See our KiCad MCP guide for the full list.

We had an AI agent build a 9 to 24 V to 5 V, 3 A buck board over seven rounds. It used tscircuit (the open-source engine Cherry Blossom runs on) with the same version and review tool as Cherry Blossom's agent, on our own machine. The rule checks earned their place. In round 1, routing was skipped because of 7 courtyard overlaps. In round 3, DRC flagged a switch-node trace 0.09 mm from a ground trace. The final build has 70 routed traces, 38 vias and 0 DRC errors, and a separate check for shorted nets found none.

DRC could not see the worst defect. Rev A passed with 0 DRC errors, but its surge clamp let 38.9 V reach a converter rated for 30 V at most. The copper was fine and a voltage rating was wrong, which is a review question, not a geometry one. A review of the datasheet ratings caught it, and rev B swapped in a 60 V converter. A later outside review found a second defect that no geometry check could see: at the datasheet's worst-case tolerances, the enable divider could stop the converter from starting on a 9 V supply. A resistor change and a zener diode fixed it.

Checks also misfire the other way. On the final board the review tool raised missing-trace warnings that were shown to be false. And a clean DRC in the design tool is still not your fab's DRC, so running the fab's own check on the exported Gerbers stays on the list for a person to do before ordering.