How to make a
schematic readable
A schematic can pass every check and still be slow to read. Here is what makes one readable, and how Cherry Blossom's blocks, Tidy and Clean up apply it, with the limits stated.
What makes a schematic readable?
A readable schematic is one where a second engineer can say what each part is for without tracing wires. It mostly comes down to six habits. They are general practice, not a standard, and they hold in any tool.
Read it like a page
Signal flows left to right, supply sits at the top, ground at the bottom. A reader should find the input, the processing and the output without following a wire.
One function, one titled group
USB input, 3.3 V power, MCU, sensor. A title says what the parts are for before anyone reads a designator.
Draw known circuits the known way
A crystal with a load capacitor to ground on each leg, a reset pull-up with its switch, a decoupling capacitor beside the supply pin it serves. An engineer recognises these at a glance and stops checking them.
Wire short runs, label long ones
A wire that crosses half the page hides what it connects, so use a net label there. A label on everything is just as bad. Keep wires for parts that sit close together.
Name the nets that matter
VBUS, 3V3, SDA and SCL read better than NET14. A made-up name is a small trap for the next person.
Split a big design into sheets
When a page needs tiny text to fit, move a function to its own sheet and show it as a box with named pins. A repeated channel becomes one sheet used twice.
These habits cost time, and they are the first thing dropped when a board is late. A schematic an AI drafts can be right and still be a pile of parts. The tools below make the readable version cheap. For how Sakura builds the circuit itself, see the AI PCB design agent.
How do blocks split a schematic into named sections?
A block is a named group of parts drawn as a thin titled frame, like the sections of an engineering sheet.
Select parts and press Ctrl+G to group them, or pick the Block tool (B) and drag a box around them, then name the block where its title sits. Ctrl+Shift+G ungroups. Dragging the title moves the whole block with what it holds, and the Inspector renames, regroups and ungroups. Sakura builds the same blocks with its group_parts and edit_block tools, and is asked to group what it adds by function.
A block stores only an id, a name and its parts. The frame is worked out from those parts, their designators and values, and the wires, labels and power ports drawn for them, so a layout pass only ever moves parts. Copy a block and it pastes as a new block around the copies.
The limit: a block is a frame, not a sheet. It has no hierarchy and no ports of its own, and a wire between two blocks stays outside both frames.
What does Tidy do to a schematic?
Tidy redraws the sheet the way an engineer would lay it out, and only when you ask. It does not change a connection.
Click the broom on the schematic toolbar, press T, or ask Sakura (its tidy_schematic tool). With one block selected the button reads “Tidy this block” and tidies just that block where it is. Otherwise it tidies the whole sheet and fits the view. It is one undo step. The shortcut reference lists the keys.
Between blocks, Tidy follows the signal. It works out reading order from the nets: the connector on the incoming supply first, then regulation by supply level, then the inputs that reach the controller on input pins, the controller, the chips it talks to, and test points last. Frames go in rows with even gutters, sized for a landscape sheet. Parts in no block land in a block named OTHER.
Inside a block, it draws known circuits to pattern. Each chip is drawn with the small parts that serve it, and these circuits get fixed layouts:
| Circuit | How Tidy draws it |
|---|---|
| Crystal | The two load capacitors hang to ground under the wires from the two crystal pins. The crystal lies across below the pins and joins both wires. |
| 555 timing network | R2, R3 and C1 stand side by side and wired, so the discharge and threshold pins are reached by wire and not by labels. |
| Reset network | A pin with two or three parts to the rails gets a straight wire out. Supply parts stand up off it, ground parts hang down. |
| Supply capacitors | A regulator's capacitors sit on its input and output wires. A chip's decoupling capacitors hang under one bus run up from its supply pins, or in rows above the chip with the supply port on top and ground below. |
Checked against the netlist. Every tidy is compared with the netlist pin for pin, net names included. If anything differs, it is refused and the project is left as it was.
Labels where wires would cross. A net that leaves its cluster, or cannot be wired cleanly, gets a label at the pin. An unnamed net that needs one is named after its most telling pin, such as U1_OUT.
Honest limits: where a connection cannot be wired cleanly Tidy uses labels, and a person might route a wire around instead. Tidying one block keeps it at its corner or the nearest free spot, and the rest of the sheet does not move to make room. A few ports still point against their rail where a pin faces away from it under a part.
How do you clean up a schematic of loose parts?
Clean up groups the parts that are in no block into named blocks, then runs Tidy on the whole sheet, as one undo step. It is free, and on Pro and Ultra there is an AI version.
The schematic toolbar has a labelled Clean up button beside the broom. Click it and nothing changes yet: a preview lists each block and how many parts it takes, with Apply and Cancel. Apply groups the parts that are in no block, tidies the whole sheet in one undo step, and fits the view. Esc cancels. On a sheet with no parts the button is disabled and says why.
Clean up (free)
Fixed rules, no model. Each small part joins the chip it is wired to most directly, so an LED follows its resistor and the chip pin, a crystal follows the clock pins, and a divider stays with its connector. The capacitors on a crowded supply go to the nearest chip on that supply. Repeated circuits, such as seven identical sensor connectors, become one block. The same sheet always gives the same groups, and blocks you made are kept.
Clean up with AI (Pro and Ultra)
Sakura reads the design and proposes blocks by function, such as USB INPUT, 3.3V POWER, MCU and SENSOR. The Sakura panel shows the plan as a card with Apply and Cancel. After you confirm, it groups and tidies as one undo step, all or nothing: if the sheet does not end up grouped and tidied as planned, nothing is committed.
Which button you see depends only on your plan: the editor asks the account whether it has managed AI. On the Free plan, or signed out, the preview ends with a pointer to Pro, and the free version still does the whole job of grouping and tidying. Plans are on the pricing page.
What else makes an AI-drawn schematic easier to read?
Sheets Sakura can build, drawing tools, KiCad-sized symbols, pins that stay on their nets, and net labels.
Hierarchical sheets, built by Sakura. It can add a sheet (or reuse one for another use of it), rename, resize and delete it, add hierarchical labels, and wire sheet pins. Each call is one undo step, and a refusal changes nothing. Its prompt suggests splitting big designs, repeated channels, and power, MCU and IO blocks. A menu beside the sheet tabs (or Ctrl+B) lists every sheet in tree order, once per use.
Drawing tools. Text, lines, arrows, polygons and rectangles, styled in a Drawing Inspector. They move with copy and paste, undo, Tidy and block drags, and Sakura can add them too. They are graphics only, and the KiCad and Circuit JSON exports leave them out and say so.
Symbols at KiCad’s proportions. Resistors, diodes, transistors and switches are drawn at KiCad’s sizes: 300 mil pin to pin for a two-terminal part, with 50 mil text. Power and ground ports follow, with names at net-label size. Older project files are migrated when they open, and a pin that would land on another net’s wire is left unconnected rather than shorted. If you are bringing a design in, see importing a KiCad project.
Pins that stay on their nets. Turning a part (R), dropping a drag, pasting, duplicating and placing a part are all checked. An edit that would join two named nets, cut a pin off its net, or leave a pin on another net’s wire is refused with a sentence saying why, and nothing changes. A part whose quarter turn is blocked goes to the next position that works, with a note.
Net labels that work. The Net label tool (L) places a label on a pin or a wire. When an edit joins a made-up NETn net to a real name, its labels are renamed in the same undo step. “Net names merged” is an electrical check you can select and ignore, and it fires only where one sheet holds both names.
All of this is in the editor now. It runs in the browser, with the AI included from the Pro plan up. The wider release is in the Cherry Blossom v2 announcement, and the editor is one click away.
Questions
A readable schematic works like a page of text. Signal flows left to right, supply is drawn at the top and ground at the bottom, and parts that do one job sit together under a title such as USB INPUT or 3.3V POWER. Standard circuits such as a crystal with its two load capacitors, a reset pull-up with its switch, and decoupling capacitors beside the pins they serve are drawn the usual way, so an engineer recognises them. Short connections are wires and long ones are net labels, important nets carry real names, and a design too big for one page is split into sheets. Cherry Blossom's blocks, Tidy and Clean up apply these habits to the schematic you already have.
Group the loose parts by function, then arrange the groups in reading order. In Cherry Blossom the Clean up button on the schematic toolbar does both. It shows a preview such as "Group 38 parts into 6 blocks and tidy the sheet?", and on Apply it groups the parts that are in no block and tidies the whole sheet as one undo step. It works on every plan. Tidy, the broom button or the T key, arranges parts that are already in blocks. Neither changes a connection: Tidy compares its result with the netlist pin for pin and leaves the project unchanged if anything differs.
The Clean up button is free. It groups parts with fixed rules and no model: each small part joins the chip it is wired to most directly, the capacitors on a crowded supply go to the nearest chip on that supply, and repeated circuits such as seven identical connectors become one block. On the Pro and Ultra plans, which include managed AI, the same button reads Clean up with AI. Sakura then proposes blocks by function, shows them as a card with Apply and Cancel, and runs the same Tidy once you confirm. Free and signed-out users see a note on the preview that the AI version comes with Pro.
It can, if the tool gives it a way to say what belongs together and a way to check the result. Sakura groups the parts it adds into named blocks by function, can build hierarchical sheets for bigger designs, and can run Tidy on its own work. Each Tidy is compared with the netlist, so a layout step cannot quietly change a connection. What AI does not remove is the need to read the result. A tidy sheet shows what the circuit is, and a person still has to confirm it is the circuit they wanted.
Yes. A sheet is drawn as a rectangle on its parent with named pins, and a double-click opens it. A sheet used twice is drawn once and listed once per use. Sakura can add, rename, resize and delete sheets, add hierarchical labels, and wire sheet pins. A menu beside the sheet tabs, or the Ctrl+B shortcut (Cmd+B on a Mac), lists every sheet in tree order. A block is a different thing: a frame around parts on one sheet, with no ports of its own.
No. The schematic drawings (text, lines, arrows, polygons and rectangles) are saved in the Cherry Blossom project but are graphics only: nothing connects to them, and the KiCad and Circuit JSON exports leave them out and say so in the export message. Net names, labels and the netlist go through as usual. If you rely on annotations surviving an export, check that message.
Try Clean up on your own schematic.
Open a project, press Clean up, read the preview, and undo it in one step if you do not like the result.
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